AccelChip and Aldec Partner to Give DSP Designers FPGA Implementation Flexibility

SCHAUMBURG, Ill.--(BUSINESS WIRE)--Nov. 12, 2002--AccelChip, Inc., the leading provider of high-level synthesis tools for DSP design; in conjunction with Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices; announced today that AccelChip's AccelFPGA tool now offers full support for Aldec's verification tools. By providing DSP users access to the most highly-performing verification tools, AccelChip and Aldec have forged a cooperative measure to best support the needs of DSP users, giving them access to manage and verify their algorithmic designs in an FPGA environment.

The majority of DSP system designers begin their design in The MathWorks, Inc. MATLAB® language so that they can much more efficiently express mathematical algorithms at the behavioral level. Once the design has been optimized in support of these algorithms, AccelChip's AccelFGPA tool effortlessly synthesizes the MATLAB models directly into optimized RTL code. AccelFPGA's high-level synthesis allows designers to reap all of the benefits of expressing their DSP designs in the MATLAB language, without having to burden themselves with worrying about the final step of physical implementation. Because AccelFPGA can translate the DSP algorithms into synthesizable RTL code, designers can now work with the newly translated models in a traditional FPGA environment and proceed as normal with an FPGA design flow, all the way through physical implementation.

Once RTL conversion has occurred, the integration between AccelFPGA and Aldec's industry-leading verification tools permits DSP designers to simulate the RTL code in Aldec's mixed language simulator without compromising any of the fast sequences that benefit DSP design. The partnership between AccelChip and Aldec permits DSP designers to verify the RTL code using the most efficient simulation technology in the industry.

AccelFPGA migrates the accuracy of DSP design into the flexibility of Aldec's integrated verification environment. All modifications, debugging and simulation can be applied in the Aldec environment as if the native code had been either VHDL or Verilog.

• "We're pleased to align ourselves with AccelChip in support of DSP designers. The integration between AccelFPGA and Aldec lets users apply a familiar FPGA environment to their algorithms. AccelChip's support of MATLAB algorithms is rapidly becoming the standard in DSP design, and we've worked closely with AccelChip to ensure that Aldec's verification tools will provide the fastest simulation runs for DSP designs," stated Stanley Hyduke, President and CEO of Aldec, Inc..
• "AccelFPGA synthesizes MATLAB into either VHDL or Verilog RTL code, so it was an easy decision to integrate AccelFPGA with Aldec's verification tools because of its common kernel simulation technology, which offers simultaneous support of both of the HDL languages that we output. This way, whether the DSP output is VHDL, Verilog, or mixed language RTL code, Aldec's tools can verify the design with a single, high-performance simulator," stated Dan Ganousis, President and CEO of AccelChip.
• "We have been very impressed with the speed, ease of use and language coverage of Aldec's Riviera simulator," said Michael A. Bohm, Chief Technical Officer of AccelChip who has been heading up the technical relationship between the two companies. "We have integrated Riviera into our simulation farm that we use for nightly regression testing and have been very pleased with the results and productivity we have achieved."

AccelChip and Aldec's partnership allows system designers to actualize a DSP design into FPGA silicon through its integrated dataflow management and simulation. AccelFPGA eliminates the need for designers to manually translate MATLAB code into RTL code, and when combined with Aldec's optimized simulation of the converted code, the tool combination shaves months off the typical DSP design cycle. Additionally, the ability to facilitate the implementation of DSP algorithms into a reprogrammable FPGA allows designer to easily re-engineer the device to support the constant changes in DSP and FPGA technology.

Availability

Both Aldec's Active-HDL 5.2 and Riviera 2002.09 tools are integrated and fully supported by both companies in an AccelFPGA flow. Active-HDL 5.2 includes Multi-Design Workspace, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. Riviera 2002.09 is based on a cross-platform, floating license that supports UNIX, Windows and Linux. All sales include one year of product maintenance. To receive your FREE evaluation copy of either Active-HDL or Riviera, contact Aldec at www.aldec.com.

About Aldec

Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs. It is recognized that to be productive in today's market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers' designs. Additional information about Aldec is available at http://www.aldec.com.

About AccelChip, Inc.

AccelChip develops and markets high-level synthesis tools that accelerate the process of chip design. Founded in 2001, the company is headquartered at 999 Plaza Drive, Suite 340, Schaumburg, IL. For more information call (847) 995-9517 or visit http://www.accelchip.com.

Active-HDL is a trademark of Aldec, Inc. AccelFPGA is a registered trademark of AccelChip. Inc. MATLAB is a registered trademark of The MathWorks, Inc. All other trademarks or registered trademarks are property of their respective owners.

     Aldec, Inc.
     Megan Moran, 702/990-4400 ext. 201
     meganm@aldec.com
     or
     AccelChip, Inc.
     Patricia Coonan, 847/995-9517 ext. 244
     patricia@accelchip.com